The present disclosure relates generally to a method and apparatus for specifying a set of instructions for selection by an instruction generator, and particularly to a method and apparatus for dynamically and conditionally specifying a set of instructions that are available for selection by an instruction stream testcase generator when choosing the next instruction to generate.
Testing of a superscalar microprocessor architecture requires the generation of a large number of instruction sequences to assure that the microprocessor behaves properly under a wide variety of circumstances. Verification techniques generally require automated testing systems that can turn out high volume testcases in an effort to sufficiently cover the realm of possible behaviors of the integrated circuit being tested. Testcases may be generated by a testcase generator in accordance with parameters specified in a file that are provided by a software design specialist or engineer, otherwise the generator generates random testcases.
Generation of instruction sequences can be pseudo-randomly selected or guided based on templates in input files that are specified by the engineer that detail the instructions to generate. Each instruction selection within a template can be an explicit instruction mnemonic, such as,                n1: LR, where the instruction LR is explicitly defined;        a control statement that guides the selection of a given list of instruction mnemonics and/or macros, such as,        Oneof(AR;AEBR;), where the control statement “Oneof” selects one explicit mnemonic from a list, such as a list of two as shown; or        a group identifier/macro that gets replaced with a control statement and/or list of mnemonics, such as,        AnyHalfOp( ) is defined as One of(LH;STH;)        Sequence(1.5 AnyHalfOp( )), where the control statement Sequence selects a random range of 1 to 5 instances of the macro.        
Control statements and macros are used to generalize the template so that various instruction combinations can be tested with only one template. Macros may be declared external to the template and imported into more than one template.
New instructions that are added to the architecture of a processor require testing, which typically involves updating macros or instruction templates previously defined, thereby enabling them to be included in the new instruction set. New macros also need to be manually created to handle new groupings of instructions, whether based on architecture attributes or user selected groupings, which typically involves listing each instruction that is a part of the newly created grouping. Occasionally, instructions need to be avoided in the testcase generation, whether due to a segmented design or an instruction that is not yet fully implemented. Additionally, each explicit mnemonic reference, control statement, or macro that uses the new instruction typically needs to be temporarily updated to remove the new instruction and then updated again when the instruction is available for testing.
Macros with large lists of instructions are storage and computationally intensive as they are expanded to create structures for each control statement and each mnemonic listed. Typically these macros are reused multiple times in an instruction stream template. When selecting instructions based on a specific state of the machine, a macro needs to be created for each instruction in this grouping and must be utilized with the corresponding initialization file to insure the existence of the specific state.
Instruction sequence generators typically have attributes associated with each instruction in the architecture. Operand characteristics can also be specified for each operand of the instruction. These are usually kept with the instruction in some table format, such as:                OP(2A) MNEM(ADR) FMT(RR) CLASS(HFP, CC_Set) . . .        OP(50) MNEM(ST) FMT(RX) CLASS(General, Store) . . .        OP(E378) MNEM(LHY) FMT(RXY) CLASS(zArch, General, Fetch, LongDisp) . . .        OP(B31A) MNEM(ADBR) FMT(RRE) CLASS(BFP, CC_Set).        
The architecture table is parsed and kept as an internal table to the generator. Use of the table facilitates testcase generation by having these instruction attributes and instruction operand characteristics readily available in a table lookup. Some of these instruction features include classifications of the instruction, that is, which class the instruction belongs to. The class identifier is a generic description for the type of instruction (such as Binary floating point), or what architecture facility it is a part of (such as Long Displacement Facility), or what format the instruction is (such RR, RRF, for example), or which architecture the instruction is valid in (such as zArch). Other instruction attributes and instruction operand attributes can be contained in the architecture table and can include instruction action (such as CC_Setter), or operand type (such as Fetch or Store).
Mnemonic specification for template guided instruction stream generation typically includes the use of explicit assembler mnemonics, control statements with a list of mnemonics, and group identifiers/macro expansion of mnemonics. Control statements guide the generation and selection of a given list of mnemonics. These control statements typically include the following types:    Sequence(n..m <substream>), which psuedo-randomly selects a number (i), such that (n<=i<=m) and creates (i) instances of <substream>;    Oneof(<substreamlist>), which psuedo-randomly selects and creates one element of the <substreamlist>;    Anyorder(<substreamlist>), which psuedo-randomly creates any permutation of the order of the items in <substreamlist>;    where,    <substream> represents either an explicit mnemonic, macro, or control statement, and    <substreamlist> represents a list of one or more <substream> elements.
As noted above, superscalar processors utilize large instruction sets that need to be tested by the production and execution of a large number of instruction sequences. To accomplish this, instruction stream testcase generators need to turn out high volume testcases in order to sufficiently cover the realm of possible behaviors of the integrated circuit being tested. Accordingly, it would be advantageous to have a testcase generator that could effectively and efficiently generate the necessary instruction stream testcases.